IPM6220ACAZ-T【PDF 8/15 页】IC REG 5OUT BUCK/LDO SYNC 24SSOP

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During the time between inductor current pulses, both the

upper and lower MOSFETs are turned off. This is referred to

as diode emulation mode because the lower MOSFET

performs the function of a diode. This diode emulation mode

prevents the output capacitor from discharging through the

lower MOSFET when the upper MOSFET is not conducting.

The gate drive is synchronized to the main clock, so the out-

of-phase timing is maintained in hysteretic mode. Such a

scheme insures a seamless transition between the

operational modes.

Operation-Mode Control

The mode-control circuit changes the converters mode of

operation based on the voltage polarity of the phase node

when the lower MOSFET is conducting and just before the

upper MOSFET turns on. For continuous inductor current,

the phase node is negative when the lower MOSFET is

conducting and the converters operate in fixed-frequency

PWM mode as shown in Figure 6. When the load current

decreases to the point where the inductor current flows

through the lower MOSFET in the reverse direction, the

phase node becomes positive, and the mode is changed to

hysteretic.

A phase comparator handles the timing of the phase node

voltage sensing. A low level on the phase comparator output

indicates a negative phase voltage during the conduction

time of the lower MOSFET. A high level on the phase

comparator output indicates a positive phase voltage.

When the phase node is positive (phase comparator high),

at the end of the lower MOSFET conduction time, for eight

consecutive clock cycles, the mode is changed to hysteretic

as shown in Figure 6. The dashed lines indicate when the

phase node goes positive and the phase comparator output

goes high. The solid vertical lines at 1,2,...8 indicate the

sampling time, of the phase comparator, to determine the

polarity (sign) of the phase node. At the transition between

PWM and hysteretic mode, both the upper and lower

MOSFETs are turned off. The phase node will ring based

on the output inductor and the parasitic capacitance on the

phase node and settle out at the value of the output voltage.

The mode change from hysteretic to PWM can be caused by

one of two events. One event is the same mechanism that

causes a PWM to hysteretic transition. But instead of looking

for eight consecutive positive occurrences on the phase

node, it is looking for eight consecutive negative

occurrences on the phase node. The operation mode will be

changed from hysteretic to PWM when these eight

consecutive pulses occur. This transition technique prevents

jitter of the operation mode at load levels close to boundary.

The other mechanism for changing from hysteretic to PWM

is due to a sudden increase in the output current. This step

load causes an instantaneous decrease in the output voltage

due to the voltage drop on the output capacitor ESR. If the

decrease causes the output voltage to drop below the

hysteretic regulation level, the mode is changed to PWM on

the next clock cycle. This insures the full power required by

the increase in output current.

Gate Control Logic

The gate control logic translates generated PWM control

signals into the MOSFET gate drive signals providing

necessary amplification, level shifting and shoot-through

protection. Also, it has functions that help optimize the IC

performance over a wide range of operational conditions.

Since MOSFET switching time can vary dramatically from

type to type and with the input voltage, the gate control logic

provides adaptive dead time by monitoring the gate-to-

source voltages of both upper and lower MOSFETs. The

lower MOSFET is not turned on until the gate-to-source

voltage of the upper MOSFET has decreased to less than

approximately 1 volt. Similarly, the upper MOSFET is not

turned on until the gate-to-source voltage of the lower

MOSFET has decreased to less than approximately 1 volt.

This allows a wide variety of upper and lower MOSFETs to

be used without a concern for simultaneous conduction, or

shoot-through.

PWM

HYSTERETIC

1 2 3 4 5 6 7 8

VOUT

PHASE

COMP

OPERATION

MODE

FIGURE 5. REGULATION IN HYSTERETIC MODE

PWM

HYSTERETIC

1 2 3 4 5 6 7 8

PHASE

COMP

OPERATION

MODE

PHASE

NODE

FIGURE 6. MODE CONTROL WAVEFORMS

IPM6220A

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